1. Field of the Invention
The present invention relates to the field of electronic circuits. More specifically, the present invention relates to a configurable glueless microprocessor interface.
2. Background Information
The Internet may be considered a global network of networks interconnected through countless numbers of network switching devices. These switching devices typically direct and/or route data from transmitting devices logically located within a first datacom/telecom network to receiving devices logically located within one or more additional datacom/telecom networks, regardless of their respective geographic locations. The Internet has undergone remarkable growth in recent years. Whether this rapid growth has resulted in the advancement of network processing technologies, or advancements in network processing technologies have in turn spurred the Internet's rapid growth, the fact remains that modern day network switching devices are continually being called upon to direct greater amounts of increasingly complex data. Accordingly, it is becoming increasingly important that network communications be carried efficiently at high speed across a wide variety of local, regional, and wide area networks, including those comprising the Internet.
When switching or routing network traffic, a need often arises to divert a portion of the data packets being routed/switched onto a particular routing path to perform additional processing (or to drop the packets), or to insert additional packets into the packet streams being received off a routing path. To provide the desired packet diversion and/or insertion functionality, one or more companion processors (also referred to as host processors) are sometimes provided. Basic implementations of these switches/routers typically route all packets through the host processor(s) to enable the host processor(s) to selectively divert some of the packets of selected ones of the various routing paths (for additional processing or dropping the packets), or to selectively inject additional packets into the packet streams of selected ones of the various routing paths. In other more advanced implementations, additional switching/routing resources (such as programmable switching/routing tables) may be employed to facilitate routing of some of the packets of selected ones of the routing paths to the host processor(s) for “processing” (“diversion”), and routing of the packets injected by the host processor(s) onto the routing paths of their selection (“insertion”). In addition to facilitating the diversion and/or insertion of packets, the host interface also allows the host processor to control the operational mode of the device, query the operational status of the device, and gain access to statistics, such as byte and packet counters, required by certain networking standards.
Host processors are often interfaced with network switching devices through various amounts of glue logic. Manufacturers and system integrators choose to utilize certain microprocessor architectures depending upon the specific functionality and features desired. For example, a first type of processor architecture (commonly available from Intel Corp., of Santa Clara, Calif.) uses a separate address and data bus for memory addressing, whereas a second type of processor architecture (commonly available from Motorola Inc., of Schaumburg, Ill.), uses a multiplexed address/data bus. A multiplexed address and data bus allows for a reduced pin count enabling a smaller component package size and therefore lower cost. The downside of a multiplexed address and data bus is that additional clock cycles are required to complete a transaction. For example, an address is typically driven onto the bus on a first clock edge, with the next clock edge signaling the beginning of one or more data phases in which data is to be transferred over the same bus. Separate address and data paths on the other hand dedicate bandwidth to each phase of the data transfer, speeding internal data handling, and resulting in higher system performance. Processors may also differ in the way they signal transactions. For example, certain types of processors utilize a transfer start indication signal in cooperation with a read/write signal to indicate the start of a read/write cycle, whereas other types of processors utilize separate read/write strobes to indicate the start of a read/write cycle.
Typically, network switching devices are designed to operate with host processors having a fixed architecture type. For example, if a network switch were designed to operate in cooperation with an Intel class processor functioning as a host processor, then simple substitution of a Motorola class host processor would not be possible without additional, and perhaps extensive glue logic being added. Accordingly, interoperability amongst processors and network switching devices is limited due to the proprietary signaling requirements of the various processors.